1. Field of the Invention
The present invention relates to a device for synchronizing a pseudo-binary signal with a clock signal into an outgoing synchronized signal.
The expression "pseudo-binary signal" hereinafter designates a logic signal having a nominal period and comprising first and second binary elements as defined hereinafter. A first binary element is signalled by first and second complementary logic levels respectively substantially during first and second successive nominal half-periods. A second binary element is signalled by the second logic level substantially during a nominal period. Moreover, a first binary element is always flanked by two second binary elements, i.e. it succeeds a second binary element and precedes another second binary element.
2. State of the Art
Two such pseudo-binary signals are produced by known bipolar-to-binary converters. The first binary elements correspond to positive polarity marks, or to negative polarity marks in a bipolar signal received by the converter.
The clock signal has a clock period substantially lower than the nominal period, and offers periodical phase jumps for the clock signal to have a mean period almost equal to the nominal period. Such a clock signal can be regenerated from a bipolar signal received by the converter as a function of a non-phase-shifted local clock signal having a period that is a sub-multiple of said regenerated clock period.
Such pseudo-binary and regenerated clock signals are notably derived in synchronizing circuits for synchronizing plesiochronous signals by means of a positive stuffing method with a view to multiplexing them in a time-division multiplexer as disclosed in U.S. Pat. No. 4,669,080.
According to the prior art, the local clock signal has a period strictly lower than the nominal half-period of the pseudo-binary signal. As a result, the phase jumps which has an amplitude equal to a fraction of the period of the regenerated clock signal, intervene during first nominal half-periods of the binary elements of the pseudo-binary signal, by means of the logic circuitry included in the synchronizing circuit. In other words, the significant instants of the regenerated clock signal, such as predetermined active transitions, usually from the second logic level "0" to the first logic level "1", in the regenerated clock signal oscillate between the limits of the first nominal half-periods in order to differentiate the binary elements.
For instance, the use of a simple bistable flip-flop synchronized by the regenerated clock signal enables the pseudo-binary signal to be reshaped into a synchronized signal. Two such flips-flops are included in the inputs of a HDB/binary transcoder included in the above-mentioned synchronizing circuit and producing a reshaped binary signal corresponding to the received bipolar signal. The flip-flop thus enables the level of the pseudo-binary signal to be read during the nominal half-periods insofar as there is identity between the binary data supported by a binary element and the logic level in the corresponding nominal first half-period.
However, such a reading is erroneous if the pseudo-binary signal is affected by a jitter such that the logic level in a first nominal half-period is different to that corresponding to the binary data. For instance, if in first binary elements of the pseudo-binary signal, the second logic level at "0" is already present from the second quarter of the nominal period on, reading will be false for any active transition of the regenerated clock signal intervening during the second quarter-period.
Furthermore, it should be emphasized that the use of the above-mentioned bistable flip-flop does not enable a correct synchronized signal to be shaped when the phase jumps of the regenerated clock signal are equal to or greater than the nominal half-period. Indeed, if an active transition of the regenerated clock signal occurs during a second nominal half-period of a binary element of the pseudo-binary signal normally corresponding to the second logic level "0", the active transition does not enable a distinction to be made as to whether the binary element is a first or second binary element.
As will be seen hereinafter, phase jumps greater than the nominal half-period may be required for the operating conditions of electrical components, especially to reconcile the operating speed of electrical components with the relatively high pseudo-binary signal rate.